1. Field of the Invention
The present invention relates generally to a multilayered chip capacitor, and, more particularly, to a multilayered chip capacitor in which a plurality of capacitors are provided in a single chip.
2. Description of the Related Art
As well known to those skilled in the art, a multilayered chip capacitor (MLCC) has a structure composed of inner electrodes interposed between a plurality of dielectric layers. The MLCC, which is advantageous because of a small size, a high capacity and easy mounting, is widely applied in various electronic devices.
Recently, to decrease the size of the part and realize an easy mounting process, there is required a multilayered chip capacitor array characterized in that two or more capacitors having the same or different electrostatic capacities are fabricated in a single chip.
FIGS. 1a and 1b are an exploded perspective view and a schematic perspective view, respectively, showing a conventional multilayered chip capacitor array.
As shown in the exploded perspective view of FIG. 1a, two first inner electrodes 12a and 12b and two second inner electrodes 13a and 13b are formed on a plurality of dielectric layers 11a and 11b, respectively. The first and second inner electrodes 12a, 12b, 13a and 13b have leads 14a, 14b, 15a and 15b extending from one lateral side thereof. The dielectric layers 11a and 11b having the first and second inner electrodes 12a, 12b, 13a and 13b shown in FIG. 1a are stacked together, to form a capacitor body 11 as shown in FIG. 1b. Further, as apparent from FIG. 1b, outer terminals 16a, 16b, 17a and 17b connected to the leads 14a, 14b, 15a and 15b are provided, thereby completing the multilayered chip capacitor 10.
As such, the first and second inner electrodes 12a and 13a at one side of the structure and the first and second inner electrodes 12b and 13b at the other side function as separate capacitors. The conventional multilayered chip capacitor array 10 depicted in FIGS. 1a and 1b includes capacitors arranged in a horizontal direction, and thus, it is difficult to decrease the size thereof when three or more capacitors are used.
In addition, the conventional multilayered chip capacitor array 10 is required to have lower equivalent series inductance (ESL), in order to be used particularly as a decoupling capacitor connected between a semiconductor chip and a power source in a power circuit of LSI.
To reduce the equivalent series inductance, U.S. Pat. No. 5,880,925 discloses a plurality of lead structures in an interdigitated arrangement of leads having opposite polarities. However, the above structure is unsuitable for use in the conventional multilayered chip capacitor arrays having a plurality of inner electrodes horizontally arranged. That is, in cases where the number of leads doubles on one lateral side of a single inner electrode in the multilayered chip capacitor array shown in FIG. 1a, it increases by two times of the number of capacitors. Thus, it is difficult to increase the number of leads in a limited space to obtain the desired ESL reduction effects.
Further, the conventional multilayered chip capacitor array is disadvantageous because the size thereof cannot decrease due to the structural restriction, and the limitation is imposed on changing the lead structure for ESL reduction.